1. Field of the Invention
The present invention relates to a semiconductor device for high-voltage and high-speed switching use as seen in an inverter, a fabricating method thereof and a flash control device using the semiconductor device.
2. Description of the Prior Art
Conventionally, an inverter with capacity up to several hundred KVA has been produced using a bipolar transistor, but a power device high in switching speed hence high in switching frequency is being sought for realizing a small-sized high-performance device. For such usage an insulated gate bipolar transistor (IGBT) has been proposed and easily realizes high-voltage and high-speed switching control up to about several tens of KHz as the IGBT has low gate drive loss characteristics.
FIG. 1 is sectional construction showing a conventional IGBT, and FIG. 2 is a circuit diagram showing an equivalent circuit thereof. In reference to FIG. 1, an n.sup.+ type semiconductor layer 102 is formed on p.sup.+ type semiconductor substrate 101 and on the layer an n.sup.- type drift layer 103 is formed. On the surface of the n.sup.- type drift layer 103 p type well regions 104 are formed by selective diffusion and on the surface of each p type well region an n.sup.+ type emitter region 105 is formed by selective diffusion. Surface portions for the p type well region 104 between the n.sup.- type drift layer 103 and the n.sup.+ type emitter regions 105 are defined as channel regions 106. Channel length is set to be around a few microns. On the channel regions 106 a gate electrode 108 is formed through a gate oxidized film 107 and on the p type well regions 104 and n.sup.+ type emitter regions 105 an emitter electrode 109 is formed. An insulation film 110 is put between the electrodes 108 and 109 to insulate them. On the back of the p.sup.+ type semiconductor substrate 101 a collector electrode 111 is formed.
In the equivalent circuit in FIG. 2, an n channel MOSFET 201 represents a MOSFET composed of vertical type MOS structure occupying a part above the n.sup.- type drift layer 104 in FIG. 1, and a pnp transistor 202 represents a bipolar transistors with p.sup.+ n.sup.+ n.sup.- p structure composed of the p.sup.+ type semiconductor substrate 101, the n.sup.+ type semiconductor layer 102, the n.sup.- type drift layer 103 and the p type well regions 104. A resistor 203 represents resistance components of the n.sup.- type drift layer 103 in FIG. 1.
When voltage between gate and emitter terminals G and E is sufficiently low and therefore MOSFET 201 is turned off, and positive bias voltage is applied between collector and emitter terminals G and E, and n.sup.- p diode between N-type drift layer 103 and the p type well regions 104 is reversely biased a depletion layer expands mainly into the n.sup.- type drift layer 103 side to form space charges so that high collector voltage can be blocked. In addition the surface of the n.sup.- type drift layer 103 can be made to have high breakdown voltage due to field plate effects by MOS structure. Accordingly to obtain a high breakdown voltage device, the n.sup.- type drift layer 103 should be designed to be lower in donor density (high resistivity) and thicker. However this easily causes the rise of the resistance value of the resistor 203 and results in a cause of lowering of current capacity.
When voltage between the collector and emitter terminals C and E is increased under condition that the MOSFET 201 is turned on by applying sufficient voltage between the gate and emitter terminals G and E, electrons flow through a channel of the MOSFET 201 from the emitter electrode 109 to the collector electrode 111. In this way a junction between a base and an emitter of the pnp transistor 202 is forward biased, the transistor 202 becomes active and a path between the collector and emitter terminals C and E of the IGBT is formed. At this time the pnp transistor 202 supplies current by amplifying drain current of the MOSFET 201. Accordingly the current capacity of the IGBT becomes higher as the amplification factor of the IGBT becomes higher as the amplification factor of the pnp transistor 202 is higher and the drain current of the MOSFET 201 is greater, also resulting in lowering of ON state voltage. However if the amplification factor of the pnp transistor 202 is raised, turn-off characteristics become poor. Though turn-off time below 1 .mu.s is required in applicating to a high-frequency inverter, if this case is realized using an IGBT of high breakdown voltage of about 1,000 V, the current amplification factor of the pnp transistor 202 must be pretty lowered. Therefore the following is devised: introduction of a life time killer by irradiation of electron beams or protons or diffusion- of heavy metals; addition of short emitter resistance to the transistor 202. As a result, in an IGBT high in speed of turn-off characteristics, there is a problem that as the current amplification factor of the pnp transistor 202 becomes less, current density cannot be raised enough for satisfying specification for the upper limit of ON state voltage.
As a method to improve trade-off between the turn-off characteristics and ON state voltage, the following has conventionally been devised as shown by 112 in FIG. 3: donor density in the vicinity of the surface of the n.sup.- drift layer 103 has been raised to lower series resistance 203 of the MOSFET 201. In addition, by virtue of this low resistance layer 112, expansion of a depletion layer advancing from the junction with the p type well regions 104 in an ON state is suppressed, so that it becomes possible for a high breakdown voltage device to be fine patterned. That is, the following is a conventional way of thinking for raising performence: since according to structure in FIG. 3 drain current can be increased by raising the current capacity of the MOSFET 201, high current density can be obtained even if the amplification factor of the pnp transistor 202 is small.
In another method to improve trade-off between turn-off characteristics and ON state voltage, a device MOSGTO is proposed. FIG. 4 is a cross-sectional view showing the structure of the MOSGTO and FIG. 5 is a circuit diagram showing the equivalent circuit thereof. In reference to FIG. 4, on a p.sup.+ type semiconductor substrate 301, an n.sup.+ type semiconductor layer 302, an n.sup.- type semiconductor layer 303 and a p type semiconductor layer 304 are piled up in this order. On the surface of the p type semiconductor layer 304 n type well regions 305 are formed by selective diffusion and on the surface of each n type well region 305 a p.sup.+ type source region 306 is formed by selective diffusion. Surface portions of the n type well regions 305 between the p type semiconductor layer 304 and the p.sup.+ type source regions 306 are defined as regions 307. On the p type semiconductor layer 304 a first gate electrode 308 is formed and on the channel regions 307 second gate electrodes 310 are formed through gate insulation films 309. Further on the n type well regions 305 and the p.sup.+ type source regions 306 cathode electrodes 311 are formed. These electrodes 308, 310 and 311 are insulated by insulation films 312. On the back of the p.sup.+ type semiconductor substrate 301 an anode electrode 313 is formed.
In an equivalent circuit in FIG. 5, a p channel MOSFET 401 represents a MOSFET composed of vertical type MOS structure of an upper portion above the p .type semiconductor layer 304 and a pnp transistor 402 represents a bipolar transistor with p.sup.+ n.sup.+ n.sup.- p structure composed of the p.sup.+ type semiconductor substrate 301, the n.sup.+ type semiconductor layer 302, the n.sup.- type semiconductor layer 303 and the p type semiconductor layer 304. An npn transistor 403 represents a bipolar transistor with n.sup.- pn structure composed of the n.sup.- type semiconductor layer 303, the p type semiconductor layer 304 and the n type well regions 305.
As regards turning on the MOSGTO, when positive bias is applied between anode and cathode terminals A and K and trigger current is flowed into a first gate terminal G1, a thyristor composed of transistors 402 and 403 is latched to open a path between anode and cathode terminals A and K. When negative voltage is applied to a second gate terminal G2 to turn the MOSFET 401 on to unlatch the thyristor, the MOSGTO is turned off.
Since this device is of thyristor structure, ON state voltage can be made low even under high voltage. However the turn-off mechanism is equivalent to a cut-off of a GTO without gate reverse bias, so that it is difficult to raise anode current enough. In addition the operability is not good because is has two gate electrodes and therefore complicated gate control is necessary for firing and cut-off. So-called MOS controlled thyristor (MCT) conducts the firing gate control of a MOSGTO by a MOS gate, but this has the same turn-off mechanism as a MOSGTO, having the same problems as the above MOSGTO.
As a device which is improved in the above difficulties and realizes high breakdown voltage, low ON resistance, high-speed turn-off and high blockable main current density, an emitter switched thyristor (EST) is proposed. FIG. 6 is a cross-sectional view showing EST structure disclosed in IEEE electron Device Letters, Vol. 11, No. 2, February 1990 "The MOS-Gated Emitter Switched Thyristor", B. Jayant Baliga. FIG. 7 is a circuit diagram showing an equivalent circuit thereof. In reference to FIG. 6, on a p.sup.+ type semiconductor substrate 501 an n type buffer layer 502, an n.sup.- type drift layer 503 and a p type base layer 504 are piled up in this order. On the surface of the p type base layer 504 an n.sup.+ type floating region 505 and an n.sup.+ type emitter region 506 are selectively formed. The surface portion of the p type base region 504 between the n.sup.+ type floating region 505 and the n.sup.+ type emitter region 506 is defined as a channel region 507. Except for the channel region 507 an p.sup.+ type region 508 is provided-surrounding the n.sup.+ type emitter region 506 to reduce base resistance. On the channel region 507 a gate electrodes 510 is formed through a gate insulation film 509 and on the n.sup.+ type emitter region 506 and the p.sup.+ type region 508 a cathode electrode 511 is formed. On the back of the p.sup.+ type semiconductor substrate 501 an anode electrode 512 is formed.
In an equivalent circuit in FIG. 7, an n channel MOSFET 601 corresponds to MOSFET composed of MOS structure above the p type base region 504 in FIG. 6 and a pnp transistor of the p.sup.+ type semiconductor substrate 501, the n type buffer layer 502, the n.sup.- type drift layer 503 and the p type base region 504. An npn transistor 603 corresponds to a bipolar transistor with n.sup.- pn.sup.+ structure composed of the n.sup.- type drift layer 503, the p type base layer 504 and te n.sup.+ type floating region 505. A resistor 604 expresses resistance component of the p type base layer 504.
For turning on this EST, it is necessary to supply the p type base layer 504 with trigger current so that the thyristor composed of the transistors 602 and 603 is made triggered and latched, under conditions that positive bias is applied across anode and cathode terminals A and K and positive voltage is applied on a gate terminal G to turn the MOSFET 601 on. Therefore as described in the above literature, a gate terminal G.sub.T used for supplying trigger current similar to the first gate terminal G1 in FIG. 4 and FIG. 5 must be suitably provided on the p type base layer 504. In an equivalent circuit in FIG. 5, this gate terminal G.sub.T is shown in a dotted line. On the other hand by making zero voltage applied on the gate terminal G to turn the MOSFET 601 off, the thyristor is unlatched and the EST is turned off.
Since the EST is, like the MOSGTO mentioned before, of thyristor structure, ON state voltage can be made low even in a high breakdown voltage case. In addition as turn-off control is made by a channel of the MOSFET 601 cascade-connected to the thyristor portion, blockable anode current is higher than the MOSGTO. Furthermore as an amplification factor of the transistor 602 can be made lower, high speed turn-off becomes possible. However since it requires two gate electrodes as the MOSGTO, there arises problems of troublesome gate control. There also arise problems that mounting density of the device lowers owing to extra gate electrodes and realizable current density becomes less.
As explained above, semiconductor devices conventionally proposed or used have respective problems. That is, an IGBT has trade-off speed and hence it is difficult to satisfy all of them. MOSGTO and MCT can realize high breakdown voltage and low ON state resistance, but there are problems that blockable main current density is low and two gate electrode are necessary so that gate control is complicated. On the other hand, EST can realize high breakdown voltage, low ON state resistance, high speed turn-off and high blockable main current density, but as two gate electrodes are necessary there are problems that gate control-is complicated,. -In addition-there also are problems that mounting density of the device cannot be increased due to extra gate electrodes.
Furthermore, as will be described later in detail, when such conventional semiconductor devices are applied to a flash control device used for a supplementary light source in taking a photograph, there are problems in flashing efficiency, making the device smaller and low-priced, so that enough satisfactory performance cannot be realized.